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Data Sheet XE3005/XE3006
VSSD VSSA VSSA VDD VREF VREG11 VREG16
Microphone Bias
XE3006
Power supply management
RESET VDDPA
AIN
Amp.
modulator
Decimator
PWM DAC
Power amplifier
AOUTP AOUTN VSSPA
SPI
Sandman Functions
Serial Audio Interface
Clock mgt
MISO SS SCK MOSI SMAD SMDA BCLK SDI SDO FSYNC MCLK
XE3005 / XE3006
Low-Power Audio CODEC
General Description
The XE3005 is an ultra low-power CODEC (Analog to Digital and Digital to Analog Converter) for voice and audio applications. It includes microphone supply, preamplifier, 16-bit ADC, 16-bit DAC, serial audio interface, power management and clock management for the ADC and the DAC. The sampling frequency of the ADC and of the DAC can be adjusted from 4 kHz to 48 kHz. The XE3006 also includes the SandmanTM function, which signals whether a relevant voice or audio signal is present for the ADC or DAC.
Features
* * * Ultra low-power consumption, below 2 mW Low-voltage operation down to 1.8 V SandmanTM function to reduce system power consumption (XE3006) Single supply voltage Adjustable sampling frequency: 4 - 48 kHz Digital format: 16 bit 2s complement Requires a minimum number of external components Easy interfacing to various DSPs Direct connection to microphone and speaker Various programming options
* * * * * * *
Applications
* * * * * * Wireless Headsets BluetoothTM headset Hands-free telephony Digital hearing instruments Consumer and multimedia applications All battery-operated portable audio devices
Quick Reference Data
* * * * * supply voltage current (@20 kHz sampling) sampling frequency Typical dynamic range ADC Typical dynamic range DAC 1.8 - 3.6 V 0.4 mA 4 - 48 kHz 78 dB 78 dB
Ordering Information
Part XE3005 XE3006 Package TSSOP 20 pins TSSOP 24 pins Ext. part no. XE3005I033 XE3006I019 Temperature range -20 to 70 C -20 to 70 C
Cool So lutions for Wire less Connectivity
XEMICS SA * e-mail: info@xemics.com * web: www.xemics.com
Data Sheet XE3005/XE3006
Table of contents
1 1.1 2 2.1 2.2 3 3.1 3.2 3.3 4 5 5.1 5.2 5.3 6 6.1 7 7.1 7.2 8 8.1 8.2 Device Description ................................................................................................................................... 3 Terminal Descriptions XE3005/6................................................................................................................ 3 Functional Description ............................................................................................................................ 4 Device Functions........................................................................................................................................ 4 Power-Down Functions ............................................................................................................................ 11 Serial Communications ......................................................................................................................... 12 Serial Audio Interface ............................................................................................................................... 12 Register Programming ............................................................................................................................. 13 Serial Peripheral Interface - SPI............................................................................................................... 14 SandmanTM Function (XE3006) ............................................................................................................. 16 Specifications ......................................................................................................................................... 18 Absolute Maximum Ratings ..................................................................................................................... 18 Recommended Operating Conditions...................................................................................................... 18 Electrical Characteristics.......................................................................................................................... 19 Application Information ......................................................................................................................... 26 Application Schematics - XE3006 ........................................................................................................... 26 Register Description .............................................................................................................................. 27 Register Functional Summary.................................................................................................................. 27 Register Definitions .................................................................................................................................. 28 Mechanical Information ......................................................................................................................... 31 XE3005 package size (TSSOP20)........................................................................................................... 31 XE3006 Package size (TSSOP24) .......................................................................................................... 32
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Data Sheet XE3005/XE3006
1 Device Description
1 2 3 4 5 6 7 8 9 MCLK SMAD SMDA VDD MOSI SS SCK MISO 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 MCLK SS VDD MOSI SCK SDI 20 19 18 17 16 15 14 13 12 11
XE3005
NRESET VREG16 VREF VSSA VSSD VREG11
SDO BCLK FSYNC AOUTP VDDPA AOUTN VSSPA
XE3006
NRESET VSSA VREG16 VREF VSSA
SDI SDO BCLK FSYNC AOUTP VDDPA AOUTN VSSPA
10 VSSD 11 VREG11 12 AIN
10 AIN
Figure 1: Pin layout of the XE3006 and XE3005 The XE3006 is available in a TSSOP24 package. The XE3005 is available in a TSSOP20 package. Detailed information is found in chapter 8, Mechanical Information.
1.1
Terminal Descriptions XE3005/6
Type 1 1 N/A N/A 3 Name MCLK SMAD SMDA VDD DI DO DO AI Description
XE3005
Terminals
XE3006
Master Clock. MCLK derives the internal clocks of ADC and DAC Sandman output ADC Sandman output DAC Digital power supply Reset signal generated by the CODEC. If required, the reset signal can 5 4 NRESET ZI/O be applied externally to initialize all the internal CODEC registers 6 N/A VSSA AI Analog ground 7 5 VREG16 AO Regulator voltage 1.6 V. Can be used to supply the microphone 8 6 VREF AO Reference voltage 9 7 VSSA AI Analog ground 10 8 VSSD AI Digital ground 11 9 VREG11 AO ADC Regulated microphone output supply voltage 1.1 V 12 10 AIN AI ADC Analog input signal 13 11 VSSPA AI DAC Power Amplifier Ground 14 12 AOUTN AO DAC Analog Output negative 15 13 VDDPA AI DAC Power Amplifier Supply 16 14 AOUTP AO DAC Analog Output positive 17 15 FSYNC DI/O Serial audio interface Frame Synchronization 18 16 BCLK DI/O Serial audio interface Bit Clock 19 17 SDO ZO Serial audio interface Data Output 20 18 SDI DI PD Serial audio interface Data Input 21 N/A MISO ZO SPI Master In Slave Out 22 19 SCK DI PD SPI Serial Clock 23 2 SS DI PU SPI Slave Select 24 20 MOSI DI PD SPI Master Out Slave In Note: (1) AI = Analog Input AO = Analog Output DI = Digital Input DO = Digital Output DI/O = Digital In or Out ZO = Hi Impedance or Output PU = internal Pull Up PD = internal Pull Down ZI/O = Hi impedance In or Out 3 D0212-116
1 2 3 4
Data Sheet XE3005/XE3006
2 Functional Description
A CODEC is typically used for voice and audio applications as an interface between a Digital Signal processor (DSP) or microcontroller and the analogue interfaces like a microphone and loudspeaker.
ADC
MIC-Amplifier
DAC
Power Amplifier
Serial Audio Interface CODEC
SPI
DSP / Microcontroller
Digital wireless transmission - BluetoothTM Voice recognition / speech synthesis
Figure 2: typical usage of CODEC This chapter provides a brief description of the CODEC features relating to the CODEC configuration. The configuration of the CODEC is defined by programming registers through a serial interface. A detailed description of the registers defining details of the CODEC setup can be found in chapter 3 and 7. Digital voice and audio samples are passed through the Serial Audio Interface.
2.1
2.1.1
Device Functions
ADC Signal Channel
The ADC channel is a chain of programmable amplifier, band-pass filter, sigma-delta modulator and a decimation filter. The amplifier gain is programmable to 5x (default) and 20x. The band-pass filter has cut-off frequencies proportional to the sampling rate. The sigma-delta modulator operates at a frequency of 64 times the sampling rate. The analog modulator is followed by a digital decimation filter. The digital output data (16 bits, 2's complement format) is made available through the Serial Audio Interface. The format of the Serial Audio interface can be selected through register J. With the default register settings the ADC can run at a sampling frequency up to 20 kHz. When used with a sampling frequency higher than 20 kHz, then register C has to be changed. The whole ADC chain can be powered-down through register I.
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Data Sheet XE3005/XE3006
2.1.2
MIC Input
The programmable pre-amplifier and the microphone bias sources VREG11 or VREG16 are optimized to operate with electret microphones. VREG11 provides a 1.1 V reference voltage. The VREG11 can deliver up to 50 A. VREG11 is enabled through control register E. VREG16 is a regulated voltage of typically 1.6V and can deliver up to 1 mA.VREG16 is always enabled.
Vcc
4 VDD NRESET VSSA VREG16 VREF VSSA VSSD VREG11
0.1F
5 6 7 8 9 10 11
12
AIN
1F
1F
820k
50 pF (gain is 5) 200 pF (gain is 20)
GND
Figure 3: typical microphone interface (1.1 V / 50 uA bias through VREG11)
Vcc
4 VDD NRESET VSSA VREG16 VREF VSSA VSSD VREG11 AIN
0.1F 1k
*
5 6 7 8 9 10 11 12
1F
*
1F
820k
50 pF (gain is 5) 200 pF (gain is 20)
depends on microphone type
GND
Figure 4: typical microphone interface (1.6 V / 1 mA bias through VREG16)
5
XE3006
XE3006
1k
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Data Sheet XE3005/XE3006
2.1.3
DAC Signal Channel
The DAC is based on a multi bit sigma-delta modulator, which operates at a frequency of 8 times the sampling rate. The outputs of the modulator are 2's complement words of 6 bit. A pulse-width modulator (PWM) converts the 6 bit words into 2 single bit streams at 256 times the sampling frequency. Finally the 2 bit streams are supplied to the power amplifier. The Power Amplifier is a Class D amplifier, which offers higher efficiency than the traditional Class AB topologies. It uses a three-state unbalanced PWM. This means that both channels of the PA (AOUTP and AOUTN) will not switch at the same time, therefore the outputs are not purely differential (see figure 5 and 6)
XE3005/6
VDDPA
From Serial Audio Interface
Interpolator & Modulator
Pulse Width Modulator
pwm_in(5:0) @ 8xFsync
P N
bit streams @ 256xFsync
P Power Amplifier P
VSSPA
N
AOUTP
dac_in(15:0) @ Fsync
N
AOUTN
s
s=1 s=0
Figure 5: DAC block diagram Figure 6 shows the relation of input and output samples of the PWM (The timing diagram is not to scale in the time-axis).
pwm_in(5:0) = 1 pwm_in(5:0) = -1 pwm_in(5:0) = 0 pwm_in(5:0) = 2
1 0 1 0 VDDPA VSSPA -VDDPA
P N
1/(256 x Fsync)
OUTP-OUTN 2/(256 x Fsync)
1/(256 x Fsync)
1/(8 x Fsync)
Figure 6: examples PWM in and out (not to scale) The DAC receives 16-bit wide 2's complement format through the Serial Audio Interface. The protocol can be selected through register J. The complete DAC and PA amplifier chain can be powered-down through register I. 6 D0212-116
Data Sheet XE3005/XE3006
2.1.4
Digital Loop Back
In digital loop back mode, the ADC output is routed directly to the DAC input. This allows in-circuit system level tests. The digital loop back mode can be selected through register J. 2.1.5 Operating Frequency
A master clock (MCLK) has to be applied to the XE3005/3006. The clock frequency of the signal applied to the MCLK pin may vary between 1.024 MHz minimum and 33.9 MHz maximum. The maximum internal clock signal frequency (MCLK/div_factor) should not exceed 12.288 MHz. The div_factor can be set by the user in register I to 1,2 or 4. The default value for div_factor is `1'. 2.1.6 Serial Audio Interface
The Serial Audio Interface is a 4-wire interface for bi-directional communication of audio data. It operates on the bit serial clock BCLK and the frame synchronization signal FSYNC. The sampling frequency of the CODEC corresponds to the rate at which the Audio Serial Interface will put out succeeding frames. One frame always corresponds to one sample. One frame always contains 2 channels. Synchronizing the Serial Audio Interface to the MCLK is recommended. FSYNC and MCLK must have a fixed ratio as defined by the following relation: FSYNC = Sampling frequency = frame rate = MCLK/(256 x div_factor). The pin BCLK defines the time when the data must be presented to the serial audio interface and shifted into (pin SDI) or out of (pin SDO) the CODEC. The number of BCLK periods in one FSYNC period is 32. The user can select to use the first 16 clock cycles (channel 1) or the second 16 clock cycles (channel 2) of BLCK to shift in or out the data samples. The table below shows some examples of the relationships between MCLK, BCLK and FSYNC MCLK 2048 kHz 8192 kHz 5120 kHz 22579.2 kHz Div_factor 1 4 1 2 BCLK 256 kHz 256 kHz 640 kHz 1411.2 kHz FSYNC 8 kHz 8 kHz 20 kHz 44.1 kHz
The table below shows the possible functional configurations of the serial audio interface CODEC master slave supported protocol LFS (long frame sync) LFS (long frame sync), SFS (short frame sync)
By default the Serial Audio Interface operates in slave, SFS mode. In slave mode the user needs to generate the signals BLCK, FSYNC and supply to the CODEC. In master mode the CODEC generates the BLCK and FSYNC signals. In that case the BLCK operates at 32 times the frequency of FSYNC. The CODEC master mode can be used with the LFS protocol only. The register J is used for the different setups of the serial audio interface.
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Data Sheet XE3005/XE3006
2.1.7
Serial Peripheral Interface - SPI
The SPI interface is used to control register values. It is a serial communications interface that is independent of the rest of the CODEC. It allows the device to communicate synchronously with a microprocessor or DSP. The CODEC interface only implements a slave controller. A detailed description can be found in chapter 3.3.
2.1.8
SandmanTM ADC Function
The SandmanTM function monitors the signals, which are processed in the ADC signal channel and the DAC signal channel. The logic output signal SMAD indicates whether the ADC signal channel has processed an audio signal or only noise, and for how long. The reference signal amplitude can be selected through register O, the time window parameters are the off time and on time (registers L, M and N).
AIN
Amp.
modulator
Serial Audio Interface Decimator Sandman Interface
FSYNC BCLK SDO
SMAD
Figure 7: Implementation of the Sandman function for the ADC (SMAD)
The logic output SMAD can be used to power-down or reduce clock speed in other devices in the application, such as a microcontroller, DSP or wireless link. Also, SMAD can be used as phone pick-up indicator. The SandmanTM function is illustrated in Figure 9 and is valid for both SMAD (related to the ADC signal) and SMDA (related to the DAC signal). Initially, SMAD is inactive (low), which means that "noise" is processed by the ADC, i.e. no audio signal amplitude above the Reference. The SandmanTM Interface compares every output sample of the ADC signal channel to the Reference value. If the signal is lower than the Reference value, SMAD remains inactive (low). As soon as the signal passes the reference (time = 1), the on-time counter is started. (for the moment defined by time='x' see Figure 9). However, as the signal returns below the reference (time = 2) before the on-time counter has reached the on time, the on-time counter is reset and the SMAD signal remains inactive (low). The next time the signal gets higher than the Reference (time = 3), the on-time counter is started again and when it reaches the on time, the SMAD signal becomes active (high), indicating that an audio signal is present (time = 4). As long as the signal remains above the Reference, nothing happens and the SMAD signal remains active (high). When the signal falls below the Reference (time = 5), the off-time counter is started, but as it does not reach the off time before the signal passes again the Reference (time = 6), SMAD remains active (high). Also during the period from time = 7 to time = 8, the off time counter does not reach the off time. When the signal falls below the Reference (time = 9) and remains below the Reference until the off-time counter has reached the off-time, the SMAD signal is changed into the inactive (low) state (time = 10).
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Data Sheet XE3005/XE3006
2.1.9
SandmanTM DAC Function
The SandmanTM function monitors the signals, which are processed in the ADC signal, channel and the DAC signal channel. The logic output signal SMDA indicates whether the DAC signal channel processes an audio signal or only noise, and this for certain duration. The reference signal amplitude can be selected through register P, the time window parameters are the off time and on time (registers L, M and N).
Reg I, bit 4 Sandman Interface SMDA VDDPA FSYNC BCLK SDI Serial Audio Interface PWM DAC Power amplifier AOUTP AOUTN VSSPA
Figure 8: Implementation of the Sandman function for the DAC (SMDA) The logic output SMDA can be employed to power-down other devices in the application, such as an external audio power amplifier. By setting bit 4 in register I, the on-chip DAC signal channel can be powered-down through SMDA too. The SandmanTM function is illustrated in Figure 9 and is valid for both SMAD (related to the ADC signal) and SMDA (related to the DAC signal).
AIN/SDO (AOUT/SDI) + reference
- reference
On-time counter
Time step = 1/fs = 1/FSYNC Off-time counter
on-time SMAD (SMDA) 12 3 4 5 6 7 8 9
off-time
10 time
Figure 9: Illustration of the SandmanTM function. The above illustration is valid for either the SMAD output as a result of AIN/SDO or for the SMDA output as a function of AOUT/SDI. 9 D0212-116
Data Sheet XE3005/XE3006
2.1.10 Start-up and Initialization The CODEC generates its own power on reset signal after a power supply is connected to the VDD pin. The reset signal is made available for the user at the pin NRESET. The rising edge of the NRESET indicates that the startup sequence of the CODEC has finished. In most applications the NRESET pin can be left open. The NRESET signal generated by the CODEC is used to initialize the various blocks in the device and guarantees a correct start-up of the circuit. The start-up sequence that is automatically carried out upon power-up of the device is listed below and illustrated in Figure 10. 1) NRESET is low (0V) when the device is not powered and remains low for a short time when VDD (upper curve in Figure 10) is applied. The low state sustains while VDD, VREG16, VREF are stabilizing. 2) As soon as the MCLK signal is present, a counter is activated that counts 221 periods of the MCLK. After this moment the NRESET is in the high state (VDD).
VDD = 1.8..3.3V VREG16 = 1.6V
VREF = 1.2V
time
MCLK
...
977 ms (MCLK=2.048KHz) NRESET main reset
Figure 10: Startup sequence and NRESET signal after power-on. The user can use the NRESET pin in 3 different ways and combinations: 1) Leave the NRESET pin not connected. In this case the CODEC will startup as described in figure 10. 2) Use the NRESET pin as an output to indicate, to e.g. a microcontroller, that the CODEC finished its power up sequence and that the CODEC is ready to operate. 3) Use the NRESET pin to force a re-initialisation of the registers to their default values. In this case the user has to force the NRESET to 0V for at least 32 periods of the MCLK. The circuit which forces the NRESET to 0V should be able to sink at least 50 uA. 10 D0212-116
Data Sheet XE3005/XE3006
Figure 11 shows the block diagram of the CODEC reset.
reset to analog and digital circuitry of codec
Power On Reset
delay delay counter MCLK XE3005/6 low drive buffer
NRESET
Figure 11: Codec reset circuitry
2.2
2.2.1
Power-Down Functions
Software Power-Down
Register I allows for the selective power down of the ADC signal channel or the DAC signal channel through SPI control. The wake-up time, after powering down the device is typically 200s. The maximum standby current is 96A, depending highly upon the Master clock (MCLK), see 5.3.5.2 Low Power Modes. 2.2.2 Hardware Power-Down
The device has no power-down pin. However, by holding down (0 V) the NRESET pin (resetting the device) as well as the pins MCLK, BCLK and FSYNC, the power consumption will reach the standby current of typically 16A. Use the standard procedure for power up (see start-up and initialization procedure) after a hardware power down and apply your registers setup procedure.
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Data Sheet XE3005/XE3006
3 Serial Communications
3.1 Serial Audio Interface
The Serial Audio Interface is a 4-wire interface for bi-directional communication of audio data. The 4 terminals are listed below: * * * * BCLK: FSYNC: SDI: SDO: Bit serial clock, one clock cycle corresponds to one data bit transmitted or received. Frame Synchronization. This signal indicates the start of a data word. The frequency of the FSYNC corresponds to the sample frequency of the CODEC. Serial Data In, data received from external device and sent to DAC. Serial Data Out, data received from ADC and sent to external device.
The same clock (BCLK) and synchronization (FSYNC) signals are used for both sending and receiving. The synchronization signal FSYNC must have a fixed ratio with the master clock signal MCLK. The Serial Audio Interface supports two formats that are commonly used for audio/voice CODECs and that are referred to as SFS (Short Frame Synchronization) and LFS (Long Frame Synchronization). Data can be transmitted and received in 2 channels. Which channel is selected depends on the programmed values in the registers. The two interface protocols are shown below.
FSYNC BCLK SDI SDO
n15 n15
channel 1, sample n
channel 2, no data
channel 1, sample n+1
n14 n14
n0 n0
-
-
-
n+115 n+115
msb
lsb
msb
Figure 12: Audio interface timing LFS mode, channel 1
FSYNC BCLK SDI SDO
n15 n15
channel 1, sample n
channel 2, sample n
channel 1, sample n+1
n14 n14
n0 n0
-
-
-
n+115 n+115
msb
lsb
msb
Figure 13: Audio interface timing in SFS mode, channel 1
SDI Data should be changed on the rising edge of BCLK. The SDI data will be read by the CODEC on the falling edge of BLCK. SDO data will change on the rising edge of the BCLK. The SDO data should be read on the falling edge of the BLCK. Each rising edge of the FSYNC indicates the start of a new sample.
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Data Sheet XE3005/XE3006
3.1.1 LFS optimization
For transmitting and receiving 32 clock cycles in one frame are always required (figure 12 and 13). This is even the case when only 16 bits have to be sent or received. In most cases this can be handled easily with a DSP and microcontroller. If the user wants to send a minimum of BLCK cycles, it is possible to shorten channel 1 (channel 2 can not be shortened). In the LFS mode the possibility exists to shorten the number of BLCK cycles to 17 instead of 32. In this case the data is transmitted and received in channel 2. Channel 1 is shortened to one BLCK cycle only. The figure 14 shows this special LFS mode.
channel 1, no data channel 1, no data channel 2, sample n channel 2, sample n+1
FSYNC BCLK SDI SDO
n15 n15 n14
n0 n0
-
n15 n15
n14 n14
n14
msb
lsb
msb
Figure 14: Audio interface timing in LFS mode,17 BLCK cycles, channel 2
3.2
Register Programming
The control registers define the configuration of the CODEC and define the various modes of operation. During power-up, all registers will be configured with default values. The control register set consists of 16 registers. A detailed description is provided chapter 7. The control registers can be changed in the two following ways: 1. Logic values at SPI pins during power-up There are 3 bits inside the registers which are configured depending on the logic values of the pins SS, SCK and MOSI during the power up startup sequence as described in section 2.1.10 Value at power up SS = 1 SS = 0 SCK = 0 SCK = 1 MOSI = 0 MOSI = 1 Influenced bits of registers Register I(0)=0 Register I(0)=1 Register J(0)=1 Register J(0)=0 Register E(2) = 0 Register E(2) = 1 comments MCLKDIV division by 1 MCLKDIV division by 2 SFS protocol LFS protocol preamplifier gain x5 preamplifier gain x20
Using the SPI pins at startup the user is able to configure the CODEC in the corresponding setups without reprogramming through the SPI interface and protocol. In best case the SPI interface can then be completely omitted and the 3 SPI pins can be fixed to `0' or `1'.
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Data Sheet XE3005/XE3006
2. Programming through SPI interface after power-up Once the device has been powered up, the configuration registers can be modified at all times (also when the device is active) through the SPI interface. The following section describes the SPI protocol which is required to change the control registers from their default values.
3.3
Serial Peripheral Interface - SPI
The serial peripheral interface (SPI) allows the device to communicate synchronously with other devices such as a microprocessor or a DSP. The CODEC interface only implements a slave controller. This section describes the communication from master (e.g. DSP) to slave (CODEC pin MOSI) and from slave (CODEC pin MISO) to a master (e.g. DSP). Four lines are used to transmit data between the slave and master: - MOSI (Master Out, Slave In) data from master to slave, synchronous with the SPI clock (SCK). - MISO (Master In, Slave Out) data from slave to master, synchronous with the SPI clock (SCK). - SCK (Serial Clock) synchronizes the data bits of MOSI and MISO. - SS (Slave Select) Slave devices are selected by activating SS.
3.3.1
Protocol
During SPI communication, data is simultaneously transmitted and received.
trecovery
SS SCK MOSI MISO
1/Fsck
tdisable
15 15
14 14
... ...
... ...
1 1
0 0
Figure 15: SPI signal timing The master puts data on the MOSI line on the falling edge of SCK; the slave reads the data on the rising edge of SCK. The slave puts data on the MISO line on the falling edge of SCK; the master reads the data on the rising edge of SCK. Transmission in either direction is by 2 bytes with MSB first. The SS pin should be kept low during the whole transfer of data. There are three timing constraints: Recovery time (t recovery) between the falling edge of SS and the falling edge of SCK. Disable time (t disable) between the last rising edge of SCK and the rising edge of SS. SCK frequency (FSCK) Min 125 2 x Tmaster Max 0.5 x Fmaster Unit ns ns Hz Comments Tmaster = clock period of the master clock MCLK Fmaster = frequency of the master clock MCLK D0212-116
Delay t recover t disable F SCK 14
Data Sheet XE3005/XE3006
3.3.2
SPI Interface Modes
There are two SPI modes: read and write. 3.3.2.1 Read Mode
Read communication always takes place in pairs of bytes. A read request of 2 bytes is sent on the MOSI line. The content of the addressed register, one byte, is dumped on the MISO line during the transmission of the second byte on the MOSI. The formats of one byte are the following: bit mosi bit miso
ss sck mosi 1 1 0 A4 A3 A2 A1 A0 1 1 0
7 1 7 msb
6 1 6
5 0 5
4 msb 4 D(7:0)
3 3
2 A (4:0) 2
1 1
0 lsb 0 lsb
request (read

)
miso
msb
lsb
read data D(7:0) of address A(4:0)
Figure 16: SPI signal timing in read mode 3.3.2.2 Write Mode
Write communication always takes place in pairs of bytes. The format of the 2 bytes is: Bit mosi Bit mosi 7 1 7 msb 6 0 6 5 0 5 4 msb 4 D(7:0) 3 3 2 A(4:0) 2 1 1 0 lsb 0 lsb
ss sck mosi
1
0
0
A4
A3
A2
A1
A0
msb
lsb
request (write to address A(4:0))
write data D(7:0) to address A(4:0)
Figure 17: SPI signal timing in write mode
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Data Sheet XE3005/XE3006
4 SandmanTM Function (XE3006)
The SandmanTM function analyzes the audio signals in the ADC and DAC. Its output signals indicate whether an audio signal is present in the ADC or DAC or if the processed signal is just noise. The threshold or reference value between noise and audio signal as well as the minimum duration of an audio signal is user-programmable through the SPI interface. If the XE3006 CODEC is used in a system that includes a microcontroller, a DSP or an RF link, the outputs of the SandmanTM Interface can be used to bring these devices into standby or sleep mode whenever no audio signal is being processed. In this way, the SandmanTM function contributes to significant additional power savings on the system level outside the XE3006 chip. The SandmanTM Interface consists of 2 digital outputs: * The SMAD detects whether the ADC processes an audio signal. The calculation is made with the digital data leaving the ADC. * The SMDA detects whether an audio signal is processed by the DAC. The calculation is made with the digital data entering through the Audio Interface. The SandmanTM Interface is implemented for the ADC and for the DAC in an identical way. It works with a set of 4 user-defined parameters: off time, on-time, ADC-reference and DAC-reference. The on time and the off time are the same for ADC and DAC. However, the reference values for the ADC and the DAC are adjusted separately, as indicated in the table below.
Input parameters Off-time1(7:0) Off-time2(15:8) On-time(7:0) ADC_reference(7:0) DAC_reference(7:0)
Register L M N O P
Sandman ADC X X X X -
Sandman DAC X X X X
The SandmanTM Interface (for the ADC as well as for the DAC) is configured with three parameters: * Reference (7:0): Absolute value under which the signal is considered noise and above which the signal is considered to be an audio signal. The SandmanTM function is disabled (SMAD or SMDA at logic 1) if this parameter is zero. The ADC and the DAC have separate Reference values. * Off-time (15:0): Time until power down. The number of sequential samples that have to be lower than the Reference for the power down signal to become active. The SandmanTM function is disabled (SMAD or SMDA at logic 1) if this parameter is zero. The ADC and DAC have one common Off-time value. * On-time (7:0): Time until wakeup. The number of sequential samples that have to be higher than the Reference for the power down signal to become inactive. The SandmanTM function is disabled (SMAD or SMDA at logic 1) if this parameter is zero. The ADC and DAC have one common On-time value. All these parameters are set in the registers L, M, N, O and P. Reference(7:0) 0 don't care don't care 1.-.255 corresponds to 128.-.32640 On-time(7:0) don't care 0 don't care 1.-.255 corresponds to 50 s - 12 ms Off-time(15:0) don't care don't care 0 1 - 65535 corresponds to 50 s - 3.2 sec Sandman (SMAD or SMDA) logic 1 (disable function) logic 1 (disable function) logic 1 (disable function) logic 1 (signal higher than ref) logic 0 (signal lower than ref) Comments Sandman disable Sandman disable Sandman disable all registers zero time for FSYNC = 20kHz
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Data Sheet XE3005/XE3006
The reference (7:0) value is related to the absolute value of the 16 bits input signal. The following format is used for the comparison: * 16 bit inputs data (2's-complement) : 0111'1111'1111'1111 = 0x7FFF * 8 bit reference (unsigned) : 0111'1111'1000'0000 = 0xFF00/2 max positive value reference max
So the reference is compared to the 8 most significant bits of the absolute value of the input signal: reference(7:0) 0 1 2 M 255 Absolute reference 0 128 256 M 255 x 128 = 32640 AIN (mV) if gain = 4 0.00 1.10 2.20 M 280 AIN (mV) if gain = 20 0.00 0.27 0.55 M 70
The values in this table are amplitude values, RMS values can be derived by dividing the numbers by 2. The working mechanism of the SandmanTM function is the following: The incoming data is compared to the reference after each time step (1/FSYNC = 50s if FSYNC = 20kHz). * During the On-time phase If the input data is higher than the reference, a counter will be incremented otherwise the counter is reset. When the counter reaches the On-time value, then the SMAD or SMDA signal is activated (high level). * During the Off-time phase If the input data is lower than the reference, a counter will be incremented otherwise the counter is reset. When the counter reaches the Off-time value, then the SMAD or SMDA signal is deactivated (low level). In a first approximation, the following points are recommended: * On-time at least 1ms. If the On-time is shorter than 1 ms, the SandmanTM function becomes sensitive to spikes in the audio input signal AIN. * Off-time at least 10ms, the Off-time should be longer than 1/fmin = 10ms, (code = 200). fmin is the minimum audio frequency = 100Hz if FSYNC = 20kHz. The value of fmin scales proportionally with the sampling frequency FSYNC. A high-pass filter in the ADC filters out signals below 100Hz. * Reference should be adjusted just above the noise level. The CODEC bandwidth is around 100 Hz to 10 kHz at the nominal system frequency settings (MCLK = 5 MHz, CKDIV = 1, FSYNC = 20 kHz). In digital loop back mode, the data entering into the Audio Interface is not transferred to the DAC. However, the SandmanTM function (if activated) continues to output the SMDA signal based on the data entered into the Audio Interface (input terminal SDI).
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Data Sheet XE3005/XE3006
5 Specifications
5.1 Absolute Maximum Ratings
Stresses above those listed in the following table may cause permanent failure. Exposure to absolute ratings for extended periods may affect device reliability. The values are in accordance with the Absolute Maximum Rating System (IEC 134). All voltages are referenced to ground (VSSA and VSSD). Analog and digital grounds are equal (VSSA = VSSD). Symbol Parameter Conditions Min Max Unit VDD Supply voltage -0.3 3.65 V Tstg Storage temperature -65 150 C TA Operating free-air temperature, TA -20 70 C Ves Electrostatic discharge protection 1) 500 V Ilus Static latchup current 2) 10 98 mA Vlud Dynamic latchup voltage 2) 50 V 1) Tested according MIL883C Method 3015.6, class JEDEC 1B (Standardized Human Body Model: 100 pF, 1500 , 3 pulses, protection related to substrate). 2) Static and dynamic latchup values are valid at 27 C.
5.2
Recommended Operating Conditions
All voltages referenced to ground (VSSA and VSSD). Min 1.8 Typ 3.0 Max 3.6 65 270 16 1.024 20 -20 32 33 48 70 Unit V mV mV Ohm MHz kHz C
Supply voltage, VDD Analog signal peak-to-peak input voltage, AIN (gain = 20x) Analog signal peak-to-peak input voltage, AIN (gain = 5x) Differential output load resistance Master clock frequency ADC or DAC conversion rate Operating free-air temperature, TA
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Data Sheet XE3005/XE3006
5.3
Electrical Characteristics
The operating conditions in this section are: VDD = 3.0 V, T = 25C. 5.3.1 Digital Inputs and Outputs, FSYNC = 20 kHz, output not loaded Parameter VOH VOL IIH IIL Ci Co High-level output voltage, DOUT Low-level output voltage, DOUT High-level input current, any digital input Low-level input current, any digital input Input capacitance Output capacitance Test Conditions IO = -360uA IO = 2mA VIH = 3.3 V VIL = 0.6 V Min 2.4 VSSD-0.5 Typ Max VDD+0.5 0.4 10 10 10 10 Unit V V uA uA pF pF
5.3.2
ADC Dynamic Performance, FSYNC = 20 kHz Parameter Test Conditions
Pre-amp gain = 5x Vin=250mV (full scale)
Min 72
Typ 78 0.5
Max
Unit dB %
SNR THD Flo Fhi GD
Signal-to-noise ratio Total harmonic distortion Low cut-off frequency (-3 dB), See Note 1 High cut-off frequency (-3 dB), See Note 2 Group delay
1/4 full scale FSYNC = 20 kHz FSYNC = 20 kHz FSYNC = 20 kHz 60
70 10
80 150
Hz kHz us
Note 1) Flo is proportional to FSYNC Note 2) Fhi equals FSYNC/2 5.3.3 ADC Channel Characteristics, FSYNC = 20 kHz Parameter Vipp Peak-to-peak input voltage (single ended) Test Conditions Pre-amp gain = 5x Pre-amp gain = 20x
A-weighted, 100 Hz-10 kHz pre-amp gain = 5x A-weighted, 100 Hz-10 kHz pre-amp gain = 20x Pre-amp gain = 5x Vin=250mV (full scale)
Min
Typ
Max 270 65 20 5
Unit mV
Vneq
Equivalent input noise Dynamic range
V rms dB dB pF MOhm [%] LSB LSB LSB LSB
72
78 60 50 200
PSRR Power supply rejection ratio, input referred Cin Rin Eg Input capacitor Input resistance VIN - VSSA gain error offset error input noise Integral non linearity Differential non linearity
Up to 1 kHz Preamp-gain = 5x Preamp gain = 20x 1 VDD 1.8-3.3V VDD 1.8-3.3V VDD 1.8-3.3V VDD 1.8-3.3V VDD 1.8-3.3V
INL DNL
+/- 0.1 -60 6.7 +/- 5 +/- 0.1
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Data Sheet XE3005/XE3006
5.3.4
DAC Dynamic Performance, load is an LC filter at 10 kHz
FSYNC = 20 kHz, MCLK = 5 MHz, for info on the LC filter see chapter 6, Application Information. Parameter SNR THD GD Signal-to-noise ratio Total harmonic distortion Dynamic range Group delay Test Conditions Bandwidth 10 kHz 1/4 full scale Bandwidth 10 kHz FSYNC = 20 kHz 72 Min 72 Typ 78 0.5 78 150 Max Unit dB % dB s
5.3.5 5.3.5.1
Power Supply Regulated supply characteristics @ T = 25C Parameter VREF reference Voltage regulated Voltage 1.1V available current output impedance regulated Voltage 1.6V available output current power supply rejection ratio, input referred power supply rejection ratio, input referred power supply rejection ratio, input referred up to 1 kHz up to 1 kHz up to 1 kHz 60 60 40 1F capacitor 820k resistor 1.5 Test Conditions 1F capacitor load Min Typ 1.2 1.1 35 1 1.6 1 50 1.5 Max Unit V V A kOhm V mA dB dB dB
VREG11 I_vreg11 R_vreg11 VREG16 I_vreg16 VREF PSRR VREG11 PSRR VREG16 PSRR 5.3.5.2
Low power mode
Stand-by mode @ VDD = 3.0V, T = 25C Parameter Istb1 Istb2 Istb3 Supply current in standby mode Supply current in standby mode Supply current in standby mode Test Conditions
ADC off, DAC off MCLK = 5 MHz, ADC off, DAC off MCLK = 12.2880 MHz NRESET mode MCLK = 0
Min
Typ 28 48 20
Max 56 96 40
Unit A A A
Stand-by mode @ VDD = 1.8V, T = 25C Parameter Istb1 Istb2 Istb3 Supply current in standby mode Supply current in standby mode Supply current in standby mode Test Conditions
ADC off, DAC off MCLK = 5 MHz, ADC off, DAC off MCLK = 12.2880 MHz NRESET mode MCLK = 0
Min
Typ 25 31 16
Max 50 62 32
Unit A A A
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Data Sheet XE3005/XE3006
5.3.5.3
Normal operation, output load consumption is not included.
Normal operations @ VDD = 3.0V, FSYNC = 20 kHz, T = 25C, Register C(7:0) = 0xF0 Parameter IDD IADC IDAC Supply current CODEC Supply current ADC Supply current DAC Test Conditions
ADC on, DAC on FSYNC = 20 kHz, no load ADC on, DAC off FSYNC = 20 kHz, no load ADC off, DAC on FSYNC = 20 kHz, no load
Min
Typ 350 240 120
Max 700 480 240
Unit A A A
Normal operations @ VDD = 3.0V, FSYNC = 48 kHz, T = 25C, Register C(7:0) = 0xC4 Parameter IDD IADC IDAC Supply current CODEC Supply current ADC Supply current DAC Test Conditions
ADC on, DAC on FSYNC = 48 kHz, no load ADC on, DAC off FSYNC = 48 kHz, no load ADC off, DAC on FSYNC = 48 kHz, no load
Min
Typ 860 600 280
Max 1720 1200 560
Unit A A A
Normal operations @ VDD = 1.8V, FSYNC = 20 kHz, T = 25C, Register C(7:0) = 0xF0 Parameter IDD IADC IDAC Supply current CODEC Supply current ADC Supply current DAC Test Conditions
ADC on, DAC on FSYNC = 20 kHz, no load ADC on, DAC off FSYNC = 20 kHz, no load ADC off, DAC on FSYNC = 20 kHz, no load
Min
Typ 250 200 65
Max 500 400 130
Unit A A A
Normal operations @ VDD = 1.8V, FSYNC = 48 kHz, T = 25C, Register C(7:0) = 0xC4 Parameter IDD IADC IDAC Supply current CODEC Supply current ADC Supply current DAC Test Conditions
ADC on, DAC on FSYNC = 48 kHz, no load ADC on, DAC off FSYNC = 48 kHz, no load ADC off, DAC on FSYNC = 48 kHz, no load
Min
Typ 625 505 140
Max 1250 1010 280
Unit A A A
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Data Sheet XE3005/XE3006
5.3.6
Timing Requirements of serial audio interface
Ref. No. *
Characteristics Master Clock Frequency for MCLK = 1/ T
MCLK Duty Cycle Rise Time for All Digital Signals Fall Time for All Digital Signals Hold time BCLK or FSYNC high after MCLK low Setup time BCLK or FSYNC high to MCLK low Hold time BCLK or FSYNC low after MCLK low Setup time BCLK or FSYNC low to MCLK low
Test Conditions
Min 1024 45
Typ 5.12
Max 33 55 10 10
Unit MHz % ns ns ns ns ns ns MHz ns ns ns ns ns
Setup time data input SDI to BCLK low Hold time data input SDI after BCLK low Delay time SDO valid after BCLK high Setup time data input FSYNC to BCLK low Hold time data input FSYNC after BCLK low *see figure 18,19 for LFS and 20, 21 for SFS
1 1 2 3 4 5 6 7 8 9 10 11 12 13
CLoad = 10pF
T/4 T/4 T/4 T/4 32xFSYNC TBCLK/4 TBCLK/4 TBCLK/4 TBCLK/4 TBCLK/4
MCLK/2
Bit Clock Frequency for BCLK = 1 / TBCLK
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Data Sheet XE3005/XE3006
5.3.6.1
Timing diagram of the serial audio interface - LFS mode
1 MCLK 5 BCLK 4 FSYNC SDI 6 7
2
3 7 6
Figure 18: LFS, timing diagram
MCLK 8 BCLK 9 FSYNC SDI SDO
D15 D14
11 10
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 19: LFS, zoom timing diagram
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D0212-116
Data Sheet XE3005/XE3006
5.3.6.2
Timing diagram of the serial audio interface - SFS mode
1 MCLK 4 BCLK FSYNC SDI 5 6 7
2
3
Figure 20: SFS, timing diagram
MCLK 8 BCLK 12 FSYNC SDI SDO 9 13
D15 D14
10
D13 D12
11
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 21: SFS zoom timing diagram
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Data Sheet XE3005/XE3006
5.3.7
Timing Requirements of the Serial Peripheral Interface
Characteristics 1 Serial Clock Frequency for SCK = 1 / TSCK MCLK Duty Cycle 1 Recovery Time 2 Disable Time 3 Setup time MISO valid to SCK high 4 Hold time MISO valid after SCK high 5 Delay time MOSI valid after SCK low 6 * see figure 22
Ref. No. *
Test Conditions
Min 45 125 2T TSCK/4 TSCK/4 TSCK/4
Typ
Max MCLK/2 55
CLoad = 10pF
Unit MHz % ns ns ns ns ns
SS SCK
2
4 5
1
3
6
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MISO MOSI
M2
M1
M0
A4
D7
D6
D5
D4
D3
D2
D1
D0
Figure 22: Serial Peripheral Interface timing
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D0212-116
Data Sheet XE3005/XE3006
6 Application Information
6.1
6.1.1
Application Schematics - XE3006
Typical Application schematic
Sandman output Master Clock
1 MCLK SMAD SMDA VDD MOSI SS SCK MISO 24 23 22 21 20 19 18 17 16 15 14 13
Vcc
2 3 4
SPI
XE3006
0.1F
5 6 7 8 9 10 11 12
NRESET VSSA VREG16 VREF VSSA VSSD VREG11 AIN
SDI SDO BCLK FSYNC AOUTP VDDPA AOUTN VSSPA
Serial Audio Interface L Vcc L L=680H 22F R 47F R R=56
1F
1F
820k
GND
lowpass filter, BluetoothTM voice application MCLK = 2.048 MHz, div_factor =1
Figure 23: Typical Application with 3rd order LC output Filter
6.1.2
External components required for optimal performances
The following minimum set-up of external components is required: * * * Capacitor for Vref: 1 F Resistor for Vref: 820 k Capacitor for VREG16: 1 F
The low pass filter between the DAC output and the speaker depends on the CODEC settings and the speaker type.
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Data Sheet XE3005/XE3006
7 Register Description
7.1 Register Functional Summary
The following registers can be programmed by the SPI to configure the operation modes. See also section 3.2 Register Programming. Name Register C Description ADC current setting. The data in this register has the following functions: * Adjust the ADC current for FSYNC > 20kHz * 0xF0 for FSYNC<= 20 kHz, 0xC4 for FSYNC > 20 kHz. Analog Input. The data in this register has the following functions: * Enable/disable microphone bias source of 1.1 V * Gain setting of pre-amplifier. Function enable and clock division. The data in this register has the following functions: * Enable/disable Sandman function of DAC * Enable/disable DAC channel (DAC, power amplifier) * Enable/disable ADC channel (pre-amplifier, ADC, decimation filter) * Division of master clock Audio Interface Configuration. The data in this register has the following functions: * Enable/disable digital loopback * Channel select receive * Select master / slave mode * Output impedance * Channel select transmit * Select short / long frame sync SandmanTM function, Off-time, low byte. The data in this register has the following function: * Define Off-time (low byte) of the SandmanTM function SandmanTM function, Off-time, high byte. The data in this register has the following function: * Define Off-time (high byte) of the SandmanTM function SandmanTM function, On-time. The data in this register has the following function: * Define On-time of the SandmanTM function SandmanTM function, reference for ADC. The data in this register has the following function: * Define reference amplitude for ADC for SandmanTM function SandmanTM function, reference for DAC. The data in this register has the following function: * Define reference amplitude for DAC for SandmanTM function
Register E
Register I
Register J
Register L Register M Register N Register O Register P
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Data Sheet XE3005/XE3006
7.2
Register Definitions
The complete register setup consists of 24 registers of 8 bits each, as shown in the table below. All registers are preconfigured with the default values and do not have to be programmed by the user if no changes in the setup are required. The registers C, E, I and J can be used to configure the XE3005 and XE3006 differently than the default setup. The registers L, M, N, O, P are related to the Sandman function available in the XE3006.
Register A B C D E F G H I J K L M N O P
Address (hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
Name Reserved Reserved ADC current Reserved Analog input Reserved Reserved Reserved Block on/off and clock division Audio interface configuration Reserved SandmanTM function, off-time byte 1 SandmanTM function, off-time byte 2 SandmanTM function, on-time SandmanTM function, reference for ADC SandmanTM function, reference for DAC
Default value (hex) 0x48 0x8F 0xF0 0x00 0x08/0x0C 0x82 0x00 0x00 0x00/0x01 0x25/0x24 0x00 0x00 0x00 0x00 0x00 0x00
Register C (7:0) address 0x02 7:0
ADC current ADC current
Default value: 0xF0 0xF0
Description 0xF0 for FSYNC<= 20 kHz, 0xC4 for FSYNC > 20 kHz.
Register E (7:0) address 0x04 7 6:3 2
ADC input VMIC_EN reserved PREAMP_ GAIN
Default value 0x08/0x0C 0 0001 0 or 1
Description Generation of the microphone supply at pin VREG11: 1: enables VREG11 0: disables VREG11 reserved Gain of preamplifier: 0: 5x (280 mV pp) 1: 20x (70 mV pp)
The default is depending on the logic value of the pin MOSI during startup (see section 3.2) MOSI=0, default will be set to 0 MOSI=1, default will be set to 1
1:0
reserved
00
reserved
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Data Sheet XE3005/XE3006
Register I (7:0) address 0x08 7:4 3 2 1:0
block on/off and clock division EN_DAC EN_ADC MCLKDIV
Default value 0x00/0x01 0000 0 0 00 or 01
Description reserved 0: enable 1: disable DA converter (DAC + PA) 0: enable 1: disable AD converter (Preamp + ADC + decimator) Division factor of the master clock: 00: 1 01: 2 10: reserved 11: 4
The default is depending on the logic value of the pin SS during startup (see Section 3.2) SS=0, default will be set to 1 SS=1, default will be set to 0
Register J (7:0) address 0x09 7 6
Audio interface configuration LOOPBACK RX_FIRST_ SECOND reserved MASTER SDO_HI_EN
Default value 0x25/ 0x24 0 0
Description
5 4 3
1 0 0
2 1 0
TX_FIRST TX_SECOND PROTOCOL
1 0 0 or 1
0: disable loopback, normal mode 1: enable loopback => The CODEC connects internally the ADC output to DAC input 0: Receive audio data in the first 16-bit channel after the frame synchronization. 1: Receive audio data in the second 16-bit channel after the frame synchronization. reserved 1: enable audio interface in master mode (only for LFS) 0: enable audio interface in slave mode (LFS or SFS) 0: SDO is continuously in output mode for both data channels. 1: SDO is in output mode when transmitting a channel with data (J(2) or J(1)=1). It is switched automatically into high-impedance state when a channel with no data is transmitted (J(2) or J(1)=0). 1: transmit the audio data in the first 16-bit channel after the frame synchronization. 0: do no transmit data in the first channel. 1: transmit the audio data in the second 16-bit channel after the frame synchronization. 0: do no transmit data in the second channel. 1: Short Frame Synchronization mode (slave mode). 0: Long Frame Synchronization mode (mode master or slave).
The default is depending on the logic value of the pin SCK during startup (see Section 3.2) SCK=0, default will be set to 1 SCK=1, default will be set to 0
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Data Sheet XE3005/XE3006
Register L (7:0) address 0x0B 7:0
SandmanTM function, off-time, least significant byte SM_OFF_LSB
Default value 0x00 00000000
Description Least significant byte of the off-time of the SandmanTM function Description Most significant byte of the off-time of the SandmanTM function Description On-time of the SandmanTM function Description Reference amplitude for ADC for SandmanTM function Description Reference amplitude for DAC for SandmanTM function
Register M (7:0) address 0x0C 7:0
SandmanTM function, off-time, most significant byte SM_OFF_MSB
Default value 0x00 00000000
Register N (7:0) address 0x0D 7:0 Register O (7:0) address 0x0E 7:0
SandmanTM function, on-time SM_ON SandmanTM function, reference for ADC SMAD_REF
Default value 0x00 00000000 Default value 0x00 00000000
Register P (7:0) address 0x0F 7:0
SandmanTM function, reference for DAC SMDA _REF
Default value 0x00 00000000
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D0212-116
Data Sheet XE3005/XE3006
8 Mechanical Information
8.1
XE3005 package size (TSSOP20)
D
E
A
X
c y HE vMA
Z
20
11
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e
1
bp
0
wM detail X
DIMENSIONS (mm are the original dim ensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D 6.6 6.4 E 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50
Q
v 0.2
w 0.13
y 0.1
Z
0.4 0.3
0.5 0.2
8 0o
o
Figure 24: TSSOP20
Plastic thin shrink small outline package; 20 leads; body width 4.4 mm
31
D0212-116
Data Sheet XE3005/XE3006
8.2
XE3006 Package size (TSSOP24)
D
E
A
X
c y HE vMA
Z
24
13
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e
1
bp
2
wM detail X
DIMENSIONS (mm are the originadimensions) l UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D 7.9 7.7 E 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z 0.5 0.2 8o 0o
Figure 25: TSSOP24
Plastic thin shrink small outline package; 24 leads; body width 4.4 mm
XEMICS, 2002 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. XEMICS PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF XEMICS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER'S OWN RISK. Should a customer purchase or use XEMICS products for any such unauthorized application, the customer shall indemnify and hold XEMICS and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise.
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D0212-116

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